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general description the ds1086 econoscillator is a programmable clockgenerator that produces a spread-spectrum (dithered) square-wave output of frequencies from 260khz to 133mhz. the selectable dithered output reduces radi- ated-emission peaks by dithering the frequency 2% or 4% below the programmed frequency. the ds1086 has a power-down mode and an output-enable control for power-sensitive applications. all the device settings are stored in nonvolatile (nv) eeprom memory allowing it to operate in stand-alone applications. applications printerscopiers pcs computer peripherals cell phones cable modems features ? user-programmable square-wave generator ? frequencies programmable from 260khz to 133mhz ? 2% or 4% selectable dithered output ? glitchless output-enable control ? 2-wire serial interface ? nonvolatile settings ? 5v supply ? no external timing components required ? power-down mode ? 10khz master frequency step size ? emi reduction ds1086 spread-spectrum econoscillator ___________________________________________________ _____________ maxim integrated products 1 pdn oe gnd 12 8 7 scl sda sprd v cc out sop/so top view 3 4 6 5 ds1086 pin configuration ordering information xtl1/osc1 micro- processor xtl2/osc2 dithered 260khz to 133mhz output decoupling capacitors (0.1 f and 0.01 f) *sda and scl can be connected directly high if the ds1086 never needsto be programmed in-circuit, including during production testing. sprd outv cc v cc v cc gnd n.c. scl* sda* pdn oe ds1086 typical operating circuit 19-6224; rev 2; 3/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: contact the factory for custom settings. + denotes a lead(pb)-free/rohs-compliant package. par emp range pin-package ds1086u 0c to +70c 8 sop ds1086u+ 0c to +70c 8 sop ds1086z 0c to +70c 8 so ds1086z+ 0c to +70c 8 so econoscillator is a trademark of maxim integrated products, inc. downloaded from: http:///
ds1086 spread-spectrum econoscillator 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions(v cc = 5v ?%, t a = 0? to +70?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.75 5.00 5.25 v high-level input voltage(sda, scl) v ih 0.7 x v cc v cc + 0.3 v low-level input voltage(sda, scl) v il -0.3 0.3 x v cc v high-level input voltage(sprd, pdn , oe) v ih 2 v cc + 0.3 v low-level input voltage(sprd, pdn , oe) v il -0.3 0.8 v dc electrical characteristics (v cc = 5v ?%, t a = 0? to +70?.) parameter symbol conditions min typ max units high-level output voltage (out) v oh i oh = -4ma, v cc = min 2.4 v low-level output voltage (out) v ol i ol = 4ma 0.4 v high-level input current i ih v cc = 5.25v 1 a low-level input current i il v il = 0v -1 ? supply current (active) i cc c l = 15pf (output at default frequency) 35 ma standby current (power-down) i ccq power-down mode 35 ? voltage on v cc relative to ground ......................-0.5v to +6.0v voltage on sprd, pdn , oe, sda, scl relative to ground (see note 1).......-0.5 to (v cc + 0.5v) continuous power dissipation (t a = +70?) ?op (derate 4.5mw/? above +70?)........................362mw so (derate 5.9mw/? above +70?) .........................470.6mw junction temperature ......................................................+150? operating temperature range...............................0? to +70? storage temperature range .............................-55? to +125? soldering temperature (reflow) lead(pb)-free................................................................+260? containing lead(pb) .....................................................+240? note 1: this voltage must not exceed 6.0v. downloaded from: http:///
ds1086 spread-spectrum econoscillator ___________________________________________________ ____________________________________ 3 master oscillator characteristics (v cc = 5v ?%, t a = 0? to +70?.) parameter symbol condition min typ max units master oscillator range f osc (note 2) 66 133 mhz default master oscillator frequency f 0 97.1 mhz default frequency (f 0 ) -0.75 +0.75 master oscillator frequencytolerance ? f 0 f 0 v cc = 5v, t a = +25 c (notes 3,17) dac step size -0.75 +0.75 % default frequency -0.75 +0.75 voltage frequency variation ? f v f 0 over voltage range,t a = +25 c (note 4) dac step size -0.75 +0.75 % default frequency -0.5 +0.5 133mhz -0.5 +0.5 temperature frequency variation ? f t f 0 over temperaturerange, v cc = 5v (note 5) 66mhz -1.0 +1.0 % prescaler bit j0 = 1 (note 6) 2 dither frequency range ? f f 0 prescaler bit j0 = 0 (note 6) 4 % integral nonlinearity of frequencydac inl entire range (note 7) -0.4 +0.4 % dac step size ? between two consecutive dac values (note 8) 10 khz dac span frequency range for one offset setting(see table 2) 10.24 mhz dac default factory default register setting 500 decimal offset step size ? between two consecutive offset values (see table 2) 5.12 mhz offset default os factory default offset register setting(5 lsbs) (see table 2) range (5 lsbs of range register) hex dither rate f 0 /4096 hz downloaded from: http:///
ds1086 spread-spectrum econoscillator 4 __________________________________________________ _____________________________________ ac electrical characteristics (v cc = 5v ?%, t a = 0? to +70?.) parameter symbol condition min typ max units frequency stable after prescalerchange 1 period frequency stable after dac oroffset change (note 9) 0.2 1 ms power-up time t p or + t stab (note 10) 0.1 0.5 ms enable of out after exitingpower-down mode t stab 500 ? out high-z after enteringpower-down mode t pdn 0.1 ms load capacitance c l (note 11) 15 50 pf output duty cycle (out) 40 60 % pdn rise/fall time 1 s ac electrical characteristics: 2-wire interface (v cc = 5v ?%, t a = 0? to +70?.) parameter symbol condition min typ max units fast mode 400 scl clock frequency f scl standard mode (note 12) 100 khz fast mode 1.3 bus free time between a stopand start condition t buf standard mode (note 12) 4.7 ? fast mode 0.6 hold time (repeated) startcondition t hd:sta standard mode (notes 12, 13) 4.0 ? fast mode 1.3 low period of scl t low standard mode (note 12) 4.7 ? fast mode 0.6 high period of scl t high standard mode (note 12) 4.0 ? fast mode 0.6 setup time for a repeatedstart t su:sta standard mode (note 12) 4.7 ? fast mode data hold time t hd:dat standard mode (notes 12, 14, 15) 0 0.9 ? fast mode 100 data setup time t su:dat standard mode (note 12) 250 ns fast mode 20 + 0.1c b 300 rise time of both sda and sclsignals t r standard mode (note 16) 20 + 0.1c b 1000 ns fast mode 20 + 0.1c b 300 fall time of both sda and sclsignals t f standard mode (note 16) 20 + 0.1c b 1000 ns downloaded from: http:///
ds1086 spread-spectrum econoscillator ___________________________________________________ ____________________________________ 5 ac electrical characteristics: 2-wire interface (continued) (v cc = 5v ?%, t a = 0? to +70?.) parameter symbol condition min typ max units fast mode 0.6 setup time for stop t su:sto standard mode 4.0 ? capacitive load for each busline c b (note 16) 400 pf nv write-cycle time t wr 10 ms input capacitance c i 5p f note 1: all voltages are referenced to ground. note 2: dac and offset register settings must be configured to maintain the master oscillator frequency within this range.correct operation of the device is not guaranteed if these limits are exceeded. note 3: this is the absolute accuracy of the master oscillator frequency at the default settings. note 4: this is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at t a = +25?. note 5: this is the percentage frequency change from the +25? frequency due to temperature at v cc = 5v. the maximum tem- perature change varies with the master oscillator frequency setting. the minimum occurs at the default master oscillatorfrequency (f default ). the maximum occurs at the extremes of the master oscillator frequency range (66mhz or 133mhz) (see figure 2). note 6: the dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. note 7: the integral nonlinearity of the frequency adjust dac is a measure of the deviation from a straight line drawn between thetwo endpoints of a range. the error is in percentage of the span. note 8: this is true when the prescaler = 1. note 9: frequency settles faster for small changes in value. during a change, the frequency transitions smoothly from the originalvalue to the new value. note 10: this indicates the time elapsed between power-up and the output becoming active. an on-chip delay is intentionallyintroduced to allow the oscillator to stabilize. t stab is equivalent to approximately 512 master clock cycles and therefore depends on the programmed clock frequency. note 11: output voltage swings can be impaired at high frequencies combined with high output loading. note 12: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device doesstretch the low period of the scl signal, it must output the next data bit to the sda line at least t r max + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released. note 13: after this period, the first clock pulse is generated. note 14: a device must internally provide a hold time of at least 300ns for the sda signal (referred to as the v ih min of the scl sig- nal) in order to bridge the undefined region of the falling edge of scl. note 15: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 16: c b ?otal capacitance of one bus line, timing referenced to 0.9 x v cc and 0.1 x v cc . note 17: typical frequency shift due to aging is ?.5%. aging stressing includes level 1 moisture reflow preconditioning (24hr+125? bake, 168hr 85?/85%rh moisture soak, and 3 solder reflow passes +240 +0/-5? peak) followed by 1000hr max v cc biased 125? htol, 1000 temperature cycles at -55? to +125?, 96hr 130?/85%rh/5.5v hast and 168hr 121?/2 atm steam/unbiased autoclave. downloaded from: http:///
typical operating characteristics (v cc = 5.0v, t a = 25 c, unless otherwise noted) ds1086 spread-spectrum econoscillator 6 __________________________________________________ _____________________________________ supply current vs. temperature ds1086 toc01 temperature ( c) current (ma) 60 50 30 40 20 10 11 12 13 14 15 16 17 18 19 2010 07 0 supply current vs. voltage ds1086 toc02 voltage (v) current (ma) 5.15 5.05 4.95 4.85 4.75 5.25 11 12 13 14 15 16 17 18 19 2010 supply current vs. prescaler ds1086 toc03 prescaler current (ma) 200 150 100 50 02 5 0 11 12 13 14 15 16 17 18 19 2010 5.25v 5.0v 4.75v supply current vs. prescaler ds1086 toc04 prescaler current (ma) 200 150 100 50 02 5 0 11 12 13 14 15 16 17 18 19 2010 70 c, 25 c, and 0 c supply current vs. temperature with oe = 0 ds1086 toc05 temperature ( c) current (ma) 60 50 30 40 20 10 1 2 3 4 5 6 7 8 9 10 0 07 0 supply current vs. temperature with pdn = 0 ds1086 toc06 temperature ( c) current ( a) 60 50 30 40 20 10 1 2 3 4 5 6 7 8 9 10 0 07 0 frequency percent change vs. supply voltage ds1086 toc07 voltage (v) frequency percent change from 5v 5.15 5.05 4.95 4.85 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 4.75 5.25 frequency percent change vs. temperature ds1086 toc08 temperature ( c) frequency percent change from 25 c 60 50 30 40 20 10 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 07 0 downloaded from: http:///
ds1086 spread-spectrum econoscillator ___________________________________________________ ____________________________________ 7 pin description pin name function 1 out oscillator output 2 sprd dither enable. when the pin is high, the dither is enabled. when the pin is low, the dither is disabled. 3v cc power supply 4 gnd ground 5o e output enable. when the pin is high, the output buffer is enabled. when the pin is low, the output isdisabled but the master oscillator is still on. 6 pdn power-down. when the pin is high, the master oscillator is enabled. when the pin is low, the masteroscillator is disabled (power-down mode). 7 sda 2-wire serial data. this pin is for serial data transfer to and from the device. the pin is open drainand can be wire-or?d with other open-drain or open-collector interfaces. 8 scl 2-wire serial clock. this pin is used to clock data into the device on rising edges and clock data outon falling edges. dithered 260khz to 133mhz output decoupling capacitors (0.1 f and 0.01 f) sprd outv cc v cc v cc 4.7k ? 4.7k ? v cc 2-wire interface gnd scl sda pdn oe ds1086 processor-controlled mode xtl1/osc1 micro- processor xtl2/osc2 dithered 260khz to 133mhz output decoupling capacitors (0.1 f and 0.01 f) *sda and scl can be connected directly high if the ds1086 never needsto be programmed in-circuit, including during production testing. sprd outv cc v cc v cc gnd n.c. scl* sda* pdn oe ds1086 stand-alone mode clock spectrum comparison (9khz bw, peak detect) ds1086 fig01 frequency (mhz) relative amplitude (dbm) 94 91 93 92 -35 -30 -25 -20 -15 -10 -5 0 -40 90 95 ds1086 no dither ds1086 4% dither crystal osc figure 1. clock spectrum dither comparison maximum temperature variation vs. master frequency frequency (mhz) frequency % change from 25 c 82.75 116.25 99.50 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 66.00 133.00 ds1086 fig02 figure 2. temperature variation over frequency downloaded from: http:///
ds1086 spread-spectrum econoscillator 8 __________________________________________________ _____________________________________ detailed description a block diagram of the ds1086 is shown in figure 3.the internal master oscillator generates a square wave with a 66mhz to 133mhz frequency range. the fre- quency of the master oscillator can be programmed with the dac register over a two-to-one range in 10khz steps. the master oscillator range is larger than the range possible with the dac step size, so the offset register is used to select a smaller range of frequencies over which the dac spans. the prescaler can then be set to divide the master oscillator frequency by 2 x (where x equals 0 to 8) before routing the signal to theoutput (out) pin. a programmable triangle-wave generator injects an off- set element into the master oscillator to dither its output 2% or 4%. the dither is controlled by the j0 bit in the prescaler register and enabled with the sprd pin. the maximum spectral attenuation occurs when the prescaler is set to 1. the spectral attenuation is reduced by 2.7db for every factor of 2 that is used in the prescaler. this happens because the prescaler? divider function tends to average the dither in creating the lower frequency. however, the most stringent spec- tral emission limits are imposed on the higher frequen- cies where the prescaler is set to a low divider ratio. the external control input, oe, gates the clock output buffer. the pdn pin disables the master oscillator and turns off the clock output for power-sensitive applica-tions*. on power-up, the clock output is disabled until power is stable and the master oscillator has generated 512 clock cycles. both controls feature a synchronous enable that ensures there are no output glitches when the output is enabled, and a constant time interval (for a given frequency setting) from an enable signal to the first output transition. the control registers are programmed through a 2-wire interface and are used to determine the output frequen- cy and settings. once programmed into eeprom, since the register settings are nv, the settings only need to be reprogrammed if it is desired to reconfigure the device. offset frequency range (mhz) os - 6 61.44 to 71.67 os - 5 66.56 to 76.79 os - 4 71.68 to 81.91 os - 3 76.80 to 87.03 os - 2 81.92 to 92.15 os - 1 87.04 to 97.27 os* 92.16 to 102.39 os + 1 97.28 to 107.51 os + 2 102.40 to 112.63 os + 3 107.52 to 117.75 os + 4 112.64 to 122.87 os + 5 117.76 to 127.99 os + 6 122.88 to 133.11 * factory default setting. os is the integer value of the 5 lsbs of the range register. register addr msb binary lsb factory default access prescaler 02h x 1 x 1 x x j0 p3 p2 p1 p0 11100000b r/w dac high 08h b9 b8 b7 b6 b5 b4 b3 b2 01111101b r/w dac low 09h b1 b0 x 0 x 0 x 0 x 0 x 0 x 0 00000000b r/w offset 0eh x 1 x 1 x 1 b4 b3 b2 b1 b0 1 1 1 - - - - - b r/w addr 0dh x 1 x 1 x 1 x 1 wc a2 a1 a0 11110000b r/w range 37h x x x x x x b4 b3 b2 b1 b0 x x x - - - - - b r write ee 3fh no data table 1. register summary x 0 = don? care, reads as zero. x 1 = don? care, reads as one. x x = don? care, reads indeterminate. x = don? care. table 2. offset settings * the power-down command must persist for at least two out- put frequency cycles plus 10? for deglitching purposes. downloaded from: http:///
ds1086 spread-spectrum econoscillator ___________________________________________________ ____________________________________ 9 the output frequency is determined by the followingequation: where: min frequency of selected offset range is the lowest frequency (shown in table 2 for the correspond-ing offset). dac value is the value of the dac register (0 to 1023). prescaler is the value of 2 x where x = 0 to 8. see the example frequency calculations section for a more in-depth look at using the registers. ________________register definitions the ds1086 registers are used to determine the outputfrequency and dither amount. a summary of the regis- ters is shown in table 1. using the default register set- tings below, the default output frequency is 97.1mhz. see the example frequency calculations section for an example on how to determine the register settings for adesired output frequency. prescaler register the prescaler register controls the prescaler (bits p3 to p0) and dither (bit j0). the prescaler divides the mas- ter oscillator frequency by 2 x where x can be from 0 to 8. any prescaler value entered that is greater than 8decodes as 8. the dither applied to the output is con- trolled with bit j0. when j0 is high, 2% peak dither is selected. when j0 is low, 4% peak dither is selected. dac high/dac low register the 2-byte dac register sets the frequency of the masteroscillator to a particular value within the current offset range. each step of the dac changes the master oscilla- tor frequency by 10khz. the first byte is the msb (dac high) and the second byte is the lsb (dac low). offset register the offset register determines the range of frequencies that can be obtained for a given dac setting. the factory default offset is copied into the range register so the user can access the default offset after making changes to the offset register. see table 2 for offset ranges. correct operation of the device is not guaranteed out- side the range 66mhz to 133mhz. f output min frequency of selected offset range dac value khz step size prescaler ( ) ( ) = + 10 sda scl 2-wire interface v cc dac offset eeprom control registers prescaler addr range sprd pdn out oe dac triangle wave generator voltage-controlled oscillator prescaler by 1, 2, 4...256 gnd master oscillator output dither signal dither control frequency control voltage ds1086 figure 3. ds1086 block diagram (1) downloaded from: http:///
ds1086 spread-spectrum econoscillator 10 _________________________________________________ _____________________________________ addr register the a0, a1, a2 bits determine the 2-wire slave address.the wc bit determines if the eeprom is to be written to after register contents have been changed. if wc = 0 (default), eeprom is written automatically after a write ee command. if wc = 1, the eeprom is only written when the write ee command is issued. in applications where the register contents are frequently written, the wc bit should be set to 1. otherwise, it is necessary to wait for an eeprom write cycle to com- plete between writing to the registers. this also pre- vents wearing out the eeprom. regardless of the value of the wc bit, the value of the addr register is always written immediately to eeprom. when the write ee command has been received, the contents of the registers are written into the eeprom, thus lock- ing in the register settings. range register this read-only register contains a copy of the factory-set offset (os). this value can be read to determine the default value of the offset register when program- ming a new master oscillator frequency. write ee command this command is used to write data from ram to eeprom when the wc bit in addr register is 1. see the addr register section for more details. example frequency calculations example #1: calculate the register values needed to generate a desired output frequency of 11.0592mhz. since the desired frequency is not within the valid mas-ter oscillator range of 66mhz to 133mhz, the prescaler must be used. valid prescaler values are 2 x where x equals 0 to 8 (and x is the value that is programmed into the p3 to p0 bits of the prescaler register). equation 1 shows the relationship between the desired frequency, the master oscillator frequency, and the prescaler. by trial and error, x is incremented from 0 to 8 in equation 2, finding values of x that yield master oscilla- tor frequencies within the range of 66mhz to 133mhz. equation 2 shows that a prescaler of 8 (x = 3) and a master oscillator frequency of 88.4736mhz generates our desired frequency. in terms of the device register, x = 3 is programmed in the lower four bits of the prescaler register. writing 03h to the prescaler register sets the prescaler to 8 (and 4% peak dither). be aware that the j0 bit also resides in the prescaler register. f master oscillator = f desired x prescaler = f desired x 2 x f master oscillator = 11.0592mhz x 2 3 = 88.4736mhz once the target master oscillator frequency has beencalculated, the value of offset can be determined. using table 2, 88.4736mhz falls within both os - 1 and os - 2. however, choosing os - 1 would be a poor choice since 88.4736mhz is so close to os - 1? mini- mum frequency. on the other hand, os - 2 is ideal since 88.4736mhz is very close to the center of os - 2? frequency span. before the offset register can be programmed, the default value of offset (os) f f prescaler f desired master oscillator master oscillator x = = 2 (2)(3) stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 4. 2-wire data transfer protocol downloaded from: http:///
ds1086 spread-spectrum econoscillator ___________________________________________________ ___________________________________ 11 must be read from the range register (last five bits). in this example, 12h (18 decimal) was read from the range register. os - 2 for this case is 10h (16 deci- mal). this is the value that is written to the offset reg- ister. finally, the two-byte dac value needs to be deter- mined. since os - 2 only sets the range of frequencies, the dac selects one frequency within that range as shown in equation 3. f master oscillator = (min frequency of selected offset range) + (dac value x 10khz) valid values of dac are 0 to 1023 (decimal) and 10khzis the step size. equation 4 is derived from rearranging equation 3 and solving for dac. since the two-byte dac register is left justified, 655 is converted to hex (028fh) and bit-wise shifted left six places. the value to be programmed into the dac reg- ister is a3c0h. in summary, the ds1086 is programmed as follows: prescaler = 03h (4% peak dither) or 13h (2% peak dither) offset = os - 2 or 10h (if range was read as 12h) dac = a3c0h notice that the dac value was rounded. unfortunately, this means that some error is introduced. in order to calculate how much error, a combination of equation 1 and equation 3 is used to calculate the expected out- put frequency. see equation 5. the expected output frequency is not exactly equal to thedesired frequency of 11.0592mhz. the difference is 450hz. in terms of percentage, equation 6 shows that the expected error is 0.004%. the expected error assumes typical values and does not include deviations from the typical as specified in the electrical tables. example #2: calculate the register values needed to generate a desired output frequency of 100mhz. since the desired frequency is already within the validmaster oscillator frequency range, the prescaler is set to divide by 1, and hence, prescaler = 00h (for 4% peak dither) or 10h (for 2% peak dither). f master oscillator = 100.0mhz x 2 0 = 100.0mhz next, looking at table 2, os + 1 provides a range offrequencies centered around the desired frequency. in order to determine what value to write to the offset register, the range register must first be read. assuming 12h was read in this example, 13h (os + 1) is written to the offset register. finally, the dac value is calculated as shown in equation 8. the result is then converted to hex (0110h) and then left-shifted, resulting in 4400h to be programmed into the dac register. in summary, the ds1086 is programmed as follows: prescaler = 00h (4% peak dither) or 10h (2% peak dither) offset = os + 1 or 13h (if range was read as 12h) dac = 4400h f mhz khz mhz mhz output (. ) ( ) . . = + = = 97 28 272 10 2 100 0 1 100 0 0 dac value mhz mhz khz step size decimal (. . ) . ( ) = = 100 0 97 28 10 272 00 % % . . . . .% error ff f error mhz mhz mhz hz mhz expected desired expected desired expected = = = = 100 11 0592 11 05875 11 0592 100 450 11 0592 100 0 004 f min frequency of selected offset range dac value x khz step size prescaler f mhz x khz mhz mhz output output ( ) ( ) (. ) ( ) . . = + = + = = 10 81 92 655 10 8 88 47 8 11 05875 dac value f min frequency of selected offset range khz step size dac value mhz mhz khz step size decimal master oscillator ( ) (. . ) . ( ) = = = 10 88 4736 81 92 10 655 36 655 (4) (8) (7) (6) (5) (9) downloaded from: http:///
ds1086 spread-spectrum econoscillator 12 _________________________________________________ _____________________________________ since the expected output frequency is equal to thedesired frequency, the calculated error is 0%. _______2-wire serial port operation 2-wire serial data bus the ds1086 communicates through a 2-wire serialinterface. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a "master." the devices that are controlled by the master are "slaves." a master device that generates the serial clock (scl), controls the bus access, and gener- ates the start and stop conditions must control the bus. the ds1086 operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines sda and scl. the following bus protocol has been defined (see figures 4 and 6): data transfer can be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changesin the data line while the clock line is high are interpreted as control signals. accordingly, the following bus conditions have beendefined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high,defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high,defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta-ble for the duration of the high period of the clock sig- nal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. sdascl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 6. 2-wire ac characteristics msb device identifier device address read/write bit 1 0 1 1 a2 a1 a0 r/w lsb figure 5. slave address downloaded from: http:///
each data transfer is initiated with a start conditionand terminated with a stop condition. the number of data bytes transferred between start and stop con- ditions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1086 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledgeafter the byte has been received. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. when the ds1086 eeprom is being written to, it is not able to perform additional responses. in this case, the slave ds1086 sends a not acknowledge to any data transfer request made by the master. it resumes normal opera- tion when the eeprom operation is complete. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figures 4, 5, 6, and 7 detail how data transfer is accomplished on the 2-wire bus. depending upon the state of the r/w bit, two types of data transfer are pos- sible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master isthe slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is trans-mitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all of the serial clockpulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition isalso the beginning of the next serial transfer, the bus is not released. the ds1086 can operate in the following two modes: slave receiver mode: serial data and clock are received through sda and scl. after each byte isreceived, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is per- formed by hardware after reception of the slave address and direction bit. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in thismode, the direction bit indicates that the transfer direc- tion is reversed. serial data is transmitted on sda by the ds1086 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. slave address figure 5 shows the first byte sent to the device. itincludes the device identifier, device address, and the r/ w bit. the device address is determined by the addr register. registers/commands see table 1 for the complete list of registers/com-mands and figure 7 for an example of using them. __________applications information power-supply decoupling to achieve the best results when using the ds1086,decouple the power supply with 0.01? and 0.1? high-quality, ceramic, surface-mount capacitors. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. these capacitors should be placed as close to pins 3 and 4 as possible. stand-alone mode scl and sda cannot be left floating when they are notused. if the ds1086 never needs to be programmed in- circuit, including during production testing, sda and scl can be tied high. the sprd pin must be tied either high or low. ds1086 spread-spectrum econoscillator ___________________________________________________ ___________________________________ 13 downloaded from: http:///
ds1086 spread-spectrum econoscillator 14 _________________________________________________ _____________________________________ chip information substrate connected to ground slave ack 10 1 1 r/w a0* a1* slave ack a2* msb lsb device identifier device address read/ write msb lsb command/register address slave ack msb lsb b7 b6 b5 b4 b3 b2 b1 b0 slave ack stop *the address determined by a0, a1, and a2 must match the address set in the addr register. data typical 2-wire write transaction example 2-wire transactions (when a0, a1, and a2 are zero) a) single byte write-write offset register b) single byte read-read offset register c) two byte write-write dac register d) two byte read-read dac register start start start start start b0hb0h b0h b0h slave ack slave ack slave ack slave ack 0eh 0eh 08h 08h slave ack slave ack slave ack slave ack data slave ack stop offset 10110000 10110000 1011000010110000 10110001 repeated start slave ack dac msb master ack dac lsb data master nack stop data b1h b7 b6 b5 b4 b3 b2 b1 b0 00001110 00001110 00001000 00001000 repeated start data offset master nack stop slave ack 10110001 b1h stop slave ack dac lsb data slave ack dac msb data figure 7. 2-wire transactions package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 ?op u8-1 21-0036 90-0092 8 so s8-4 21-0041 90-0096 downloaded from: http:///
ds1086 spread-spectrum econoscillator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. 15 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision da te description pages changed 0 10/02 initial release 1 9/03 corrected the dither rate in the master oscillator characteristics table; updated table 2 3, 8 2 3/12 updated the ordering information , absolute maimum ratings , and package information 1, 2, 14 downloaded from: http:///

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